Delta Tau PMAC2 PCI User Manual download pdf (Page 91)

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PMAC2 User Manual

PMAC2 General Purpose I/O Use 83

The -12V and matching +12V supply voltages are available on the J1 connector to supply the analog

circuitry providing the signals. The +12V supply is not used by PMAC2; it is merely passed through to

the J1 connector for convenience. If use of this supply is desired, it must either come from the bus supply

through PMAC2’s bus connector, or from TB1.

Multiplexing Principle

Only one pair of analog-to-digital converter registers is available to the PMAC2 processor at any given

time. The data appears to the processor at address Y:$FFC0. The data from the selected analog input 0 to

7 (ANAI00-ANAI07) appears in the low 12 bits; the data from the selected analog input 8 to 15

(ANAI08-ANAI15) appears in the high 12 bits (this data is only present if Option 12A has been ordered).

The input is selected and the conversion is started by writing to this same word address Y:$FFC0. A

value of 0 to 7 written into the low 12 bits selects the analog input channel of that number (ANAI00-

ANAI07) to be converted in unipolar mode (0V to +5V). A value of 0 to 7 written into the high 12 bits

selects the analog input channel numbered 8 greater (ANAI08-ANAI15) in unipolar mode. If the value

written into either the low 12 bits or the high 12 bits is 8 higher (8 to 15), the same input channel is

selected, but the conversion is in bipolar mode (-2.5V to +2.5V).

Analog Data Table

PMAC2 firmware automatically selects and reads the channels of the A/D converters in a round-robin

fashion. This function is controlled by a data table (reference Table 10-1) in registers $0708 to $070F

which operates much like the encoder conversion table. The eight X registers contain the channel select

information, and the eight Y registers contain the A/D results. Each X and Y word is split into two 12-bit

halves, where the lower 12 bits work with the first A/D converter set (Option 12), and the higher 12 bits

work with the second A/D converter set (Option 12A).

PMAC2 Address X Word

Upper 12 Bits

X Word

Lower 12 Bits

Y Word

Upper 12 Bits

Y Word

Lower 12 Bits

$0708 CONFIG_W2 CONFIG_W1 DATA_W2 DATA_W1

$0709 CONFIG_W2 CONFIG_W1 DATA_W2 DATA_W1

$070A CONFIG_W2 CONFIG_W1 DATA_W2 DATA_W1

$070B CONFIG_W2 CONFIG_W1 DATA_W2 DATA_W1

$070C CONFIG_W2 CONFIG_W1 DATA_W2 DATA_W1

$070D CONFIG_W2 CONFIG_W1 DATA_W2 DATA_W1

$070E CONFIG_W2 CONFIG_W1 DATA_W2 DATA_W1

$070F CONFIG_W2 CONFIG_W1 DATA_W2 DATA_W1

where:

• CONFIG_W2 is the selection word for the second A/D converter set (Option 12A)

• CONFIG_W1 is the selection word for the first A/D converter set (Option 12)

• DATA_W2 is the matching A/D data from the second A/D converter set (Option 12A)

• DATA_W1 is the matching A/D data from the first A/D converter set (Option 12)

• A value of 0-7 in CONFIG_W1 tells PMAC2 to read channel ANAI00-07, respectively, as a 0 to+5V

input.

• A value of 8-15 in CONFIG_W1 tells PMAC2 to read ANAI00-07, respectively, as a -2.5 to +2.5V

input.

• A value of 0-7 in CONFIG_W2 tells PMAC2 to read channel ANAI08-15, respectively, as a 0 to+5V

input.

• A value of 8-15 in CONFIG_W1 tells PMAC2 to read ANAI08-15, respectively, as a -2.5 to +2.5V

input.

Each phase update (9 kHz default), PMAC2 increments through one line of the table. It copies the ADC

readings selected in the previous cycle into RAM, then writes the next configuration words to the ADCs.

Typically, this will be used to cycle through all eight ADCs or pairs of ADCs.

1 2 ... 86 87 88 89 90 91 92 93 94 95 96 ... 100 101

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Delta Tau PMAC2 PCI User Manual Page 91

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